This invention relates to a planar semiconductor device having high breakdown voltage.
A planar pn junction diode having high breakdown voltage is disclosed in "HIGH VOLTAGE THIN LAYER DEVICES (RESURF DEVICES)" by J. A. Appels et. al. in IEEE IEDM Technical Digest, December 1979, pp. 238-241. The device is constructed by using a so-called RESURF technology. With the device of this construction, A layer having high impurity concentration is surrounded by a layer having low impurity concentration with the same conductivity type as the low impurity concentration layer is formed to have an impurity concentration of approx. 2.times.10.sup.12 /cm.sup.2 so as to provide an extremely high breakdown voltage.
Thus, the device can be formed to have high breakdown voltage, but when it is subjected to a BT test (Bias-temperature test) which is effected by application of reverse bias voltage at a high temperature, the breakdown voltage is deteriorated to a greater extent. It is understood that this may be caused by the movement of charges, particularly plus ions in a SiO.sub.2 film covering the surface of the device. That is, when a reverse bias voltage is continuously applied at a temperature of approx. 150.degree. C., a depletion layer is created in the semiconductor layer and a strong electric field is set up in the surface area of the semiconductor layer, moving the charges in the SiO.sub.2 film and concentrating them into one place. As a result, the electric field is generated by the concentration of charges, resultantly intensifying the electric field in the depletion layer created near the surface of the semiconductor layer. Thus, the breakdown voltage is lowered.
Further, in this device, when the impurity concentration of the low impurity concentration layer surrounding the high impurity concentration layer is high, it becomes impossible to attain a high breakdown voltage. This is because the low impurity concentration layer surrounding the high impurity concentration layer is not completely depleted when the pn junction is reversely biased, and the electric field is concentrated at the curved portion of the pn junction with a small curvature. For this reason, the optimum value of the impurity concentration of the low impurity concentration layer is set to 2.times.10.sup.12 to 4.times.10.sup.12 /cm.sup.2. Thus, the range of the impurity concentration is set narrow, making small the allowance for dose amount used in the manufacturing process.
A device is known in which the electric field is prevented from being concentrated in the surface of the semiconductor layer by forming SIPOS (Semi-insulating Polycrystalline Silicon) directly on the surface of the semiconductor layer. Such a device is disclosed in, for example, "Highly Reliable High-Voltage Transistor by Use of the SIPOS Process" by T. MATSUSHITA et. al. in IEEE Trans. Electron Devices, Vol. ED-23, No. 8, August 1976 pp. 826-830. The SIPOS functions not only to prevent the concentration of electric filed but also to shield the semiconductor substrate from the external electric field.
Further, "Design Optimization of 1000V Resistive Field Plate" by K. WATANABE et al. in The Transactions of the IECE of Japan, Vol. E69, No. 4 April 1986 pp. 246-247 discloses the technology of forming a RFP (Resistive Field Plate) over the semiconductor layer through an oxidation film. In operation of the semiconductor device, a voltage applied to the semiconductor device is applied across the RFP to conduct a current therethrough, thus setting up a linear potential gradient in the RFP. With the RFP, the curvature of the depletion layer created in the surface area of the semiconductor layer can be made large, attaining a high breakdown voltage. Like the SIPOS, the inventors found that the RFP has an effect of shielding the external electric field. For example, wiring layers (i.e. interconnection metal layers) will be formed on the RFP in an IC device, but the RFP functions to shield the external electric field generated by the wiring layers, thus preventing the semiconductor substrate from being affected by the external electric field.
However, there still remains a problem that only 70% of the theoretical breakdown voltage determined by the semiconductor substrate or bulk can be attained when the SIPOS or RFP is used.